Endless Memory with CXL®: A Recap
The AI Leadership Forum, managed by IT Brand Pulse, hosted the first episode of the Endless Memory with CXL® series on September 30, 2026. The speakers came from an analyst firm and companies actively involved in CXL implementations, and this first episode set the stage for the sessions to follow. This episode examined why AI needs so much memory, the supply and cost pressures around DRAM, and practical ways of closing the gap.
RoCE v2: RDMA over Converged Ethernet for AI-Scale Networking
A GPU cluster with terabytes of pooled memory and blistering local bandwidth is only as good as the fabric that lets thousands of those GPUs exchange gradients, activations, and KV cache fragments with each other in microseconds. That fabric, for a large and growing share of AI training and inference clusters, runs on RDMA over Converged Ethernet version 2, or RoCE v2.
ROCm: AMD's Open-Source Path Through the AI Software Stack
But an AI accelerator is only as useful as the software that lets it run a model, and for AMD's Instinct GPUs, ROCm is that software. If CUDA is the reason NVIDIA's hardware advantage has proven so durable, ROCm is AMD's answer to the same problem: how do you get PyTorch, vLLM, and a few hundred thousand developers to treat your silicon as a first-class citizen rather than an afterthought.
Co-Packaged Optics: Moving Light Closer to Silicon
As port speeds climbed from 400G to 800G to 1.6T, the electrical trace between the switch ASIC and the front-panel optical module got harder to drive without burning power on retimers and losing signal to trace loss. Co-Packaged Optics, or CPO, attempts to move the optics off the front panel and onto the same package as the switch or compute die, so the electrical path nearly disappears.
NVMe for AI Workloads
This article examines why NVMe has become foundational to modern AI workloads, the technical developments driving its adoption, and the considerations organizations should weigh when architecting AI storage systems.
NVHBM: NVIDIA's Custom High Bandwidth Memory Architecture for Semi-Custom AI Silicon
Recently, NVIDIA introduced a new architecture, called NVHBM, which pulls the memory controller out of the XPU chip and puts it inside the HBM stack's own base die. Amazon's Annapurna Labs is already on board for Trainium4.
Semicon 2.0: India's Next Phase in the Global Chip Race
On July 15, 2026, the Union Cabinet approved Semicon 2.0, the second phase of India's semiconductor policy, with a fiscal outlay of ₹1,27,500 crore (roughly $13.3 billion). While the numbers look good, I believe it’d be good to look at what Semicon 2.0 actually proposes, how it builds on its predecessor, and where there are gaps, still.
InfiniBand vs. Ethernet
If compute is the engine of AI infrastructure, the network is the nervous system. It's time to turn to the two standards that carry data between servers and racks: InfiniBand and Ethernet.
What's this buzz around Kimi K3
In mid-July 2026, a Beijing-based startup most people outside AI circles had never heard of released what it calls the largest “open-weight” AI model in the world, meaning the trained model itself, not just access to it through an app or API, is available for anyone to download and run, and for a few days it became the biggest story in the industry.
HBM4: JEDEC's Next-Generation High Bandwidth Memory Standard
HBM4 is JEDEC's answer, standardized as JESD270-4 in April 2025 with input from AMD, Nvidia, Google, SK hynix, Samsung, Micron, and other major players. It roughly doubles per-stack bandwidth over HBM3, and it does something more interesting than just “go faster”: it fundamentally changes who gets to design part of the memory stack.
UALink vs NVLink: Can the Industry Out-Link Nvidia?
UALink defines an open, memory-semantic, scale-up interconnect that allows accelerators to perform load, store, and atomic operations across the fabric, not merely send messages to each other.
StorageAI: Giving Storage a Seat at AI's Table
SNIA announced StorageAI on August 4, 2025, describing it as an open standards project for efficient data services related to AI workloads, built on industry-standard, non-proprietary, vendor-neutral approaches.
Houston, We Have a Data Center: AI Infrastructure Goes Orbital
Over the past few months, the AI infrastructure conversation has taken an unmistakable turn: upward.
ESUN: Ethernet Walks Into the Rack and Says "I Can Do That Too"
ESUN's charter, deliberately narrow: define open, standards-based Ethernet switching and framing for scale-up networking.
ZAM: Intel and SoftBank's Bold Bet on the Memory Front
ZAM is a stacked DRAM architecture, conceptually similar to HBM but with a fundamentally different approach to how the layers are connected and how heat escapes.
CXL is Alive and Kicking!
In this article, I will talk about some of the recent CXL implementations, most of them geared to serve the insatiable appetite of AI compute infrastructure.
SOCAMM: Yet Another Framework on the Memory Horizon
The SOCAMM memory leverages the LPDDR5X memory, which, as the name states, is a Low Power memory. However, LPDDR is a soldered-down memory leaving no room for repair and field-replaceability; thereby increasing the total cost of ownership. (TCO) SOCAMM is a screws-secured, socketed memory
Crumbling the Memory Wall with High Bandwidth Flash (HBF)
Enters High Bandwidth Flash or HBF, which aims to serve as an intermediary layer between HBM and the slower NVMe SSDs. The base architectural concept remains similar to HBM.Enters High Bandwidth Flash or HBF, which aims to serve as an intermediary layer between HBM and the slower NVMe SSDs. The base architectural concept remains similar to HBM.