ZAM: Intel and SoftBank's Bold Bet on the Memory Front
Another new entrant on the memory horizon — and this one comes with national laboratory credentials, diagonal copper interconnects, and an ambition to become an alternative to HBM.
I have been writing about memory frameworks that matter for AI infrastructure — CXL, HBF, SOCAMM. Each one attempts to chip away at the memory wall in its own way. Today, it is the turn of ZAM, short for Z-Angle Memory, a collaboration between Intel and SoftBank subsidiary SAIMEMORY that has been generating considerable buzz since its announcement in February 2026.
ZAM is interesting not just as a technology, but also as a geopolitical and strategic statement. Frankly, I hate the “geopolitics” part that gets into the technology realm. But “geopolitics” has long crept in any resource with potential. More on that shortly. First, the usual orientation: why does any of this matter?
Why Memory Keeps Screaming for Attention
The AI era has a memory problem that does not go away. Every generation of GPU compute outpaces memory supply. High Bandwidth Memory (HBM) emerged as the answer — DRAM dies stacked vertically, connected via Through-Silicon Vias (TSVs), placed right next to the GPU die on a silicon interposer. HBM dramatically shortens the data path and increases bandwidth.
But HBM has its own walls now. The supply is tightly controlled by three players — Samsung, SK hynix, and Micron — and demand from AI hyperscalers far outpaces production. HBM is costly. Memory shortages are expected to persist into 2027. And on the technical side, stacking more layers in HBM introduces serious thermal bottlenecks; heat gets trapped in the center of the stack, limiting clock speeds and efficiency.
This is the landscape into which ZAM steps.
What is Z-Angle Memory?
ZAM is a stacked DRAM architecture, conceptually similar to HBM but with a fundamentally different approach to how the layers are connected and how heat escapes.
The key innovation is what Intel calls the "Via-in-One" construct. Traditional HBM relies on thousands of TSVs drilled through the center of each DRAM die — like installing vertical elevators scattered across the floor plan of a high-rise building. Each TSV requires a Keep-Out Zone where no active transistors can exist, consuming silicon area. As stacks get taller (12-Hi, 16-Hi, and beyond), the middle dies become thermal dead zones.
ZAM takes a different route. Rather than a distributed TSV field, ZAM uses a consolidated connection structure at the periphery of the stack, with copper interconnects routing through in a Z-shaped diagonal path. Think of it less like scattered elevators and more like diagonal escalators that also conduct heat outward. The center of the memory bank becomes a solid, monolithic block of DRAM silicon — thermally superior, and more efficient in its use of die area.
The technology builds on Intel’s Next Generation DRAM Bonding (NGDB) initiative, itself developed under the US Advanced Memory Technology (AMT) program managed by the Department of Energy through Sandia, Lawrence Livermore, and Los Alamos National Laboratories. These are not casual research pedigrees.
Technical Specifications (What We Know)
At the 2026 IEEE/JSAP VLSI Symposium in Honolulu, researchers from SAIMEMORY, Intel, Powerchip Semiconductor Manufacturing (PSMC), and AP Memory jointly presented a nine-layer 3D high-bandwidth DRAM structure. Here is what the paper revealed:
Nine layers: one logic base die and eight DRAM storage layers stacked on top
Each DRAM layer is only 3 microns of silicon substrate — extremely thin
Each DRAM layer holds approximately 1.125 GB, giving roughly 9–10 GB total per module
Approximately 13,700 via-in-one TSVs per layer using fusion bonding (hybrid bonding)
Bandwidth density of approximately 0.25 Tb/s per mm², which translates to roughly 5.3 TB/s per stack at a die area of 171 mm²
Data movement energy below 0.7 picojoules per bit
Data transmission power under 0.35 W/mm²
Functional verification and reliability testing confirmed within 0.95–1.2 V range
For context, HBM4 delivers around 2 TB/s per stack. ZAM’s claimed 5.3 TB/s per stack, if validated at scale, is a significant leap. The capacity per module, however, is more modest at this stage — HBM4 already achieves tens of gigabytes per stack, so ZAM has ground to cover on the capacity front.
What Makes ZAM Different: The USP
Thermal advantage
This is the headline claim. ZAM’s vertical Z-angle architecture is said to enable continuous thermal conduction paths through each memory slice, allowing heat to escape outward rather than building up in the core of the stack. Intel and SAIMEMORY claim 40–50% lower power consumption compared to conventional HBM. For AI data centers already grappling with soaring energy bills and cooling challenges, this is not a trivial number.
Higher bandwidth density
The elimination of the central TSV field theoretically reclaims silicon area, and the Via-in-One construct enables a more direct electrical path. The claimed bandwidth density of ~0.25 Tb/s/mm² exceeds what HBM4 currently offers.
Supply chain diversification
PSMC in Taiwan handles manufacturing, US national labs contributed foundational research, Japan’s government is co-funding commercialization, and Intel brings bonding technology and patents. It is explicitly a US-Japan-Taiwan counter to Korean HBM dominance.
A Dose of Realism
ZAM sounds promising, but it is still paper and early prototype territory. A few grounding observations:
Capacity gap: The first ZAM module delivers ~9–10 GB per stack. HBM4 already hits tens of gigabytes. This gap needs to close before ZAM can serve the same workloads.
Manufacturing yield: Stacking eight thinned DRAM dies without defects is an unproven industrial challenge at scale. HBM vendors have iterated on this for a decade. ZAM has not.
Funding scale: SoftBank’s ~$20 million investment is early-stage R&D money. HBM vendors invest billions annually in capacity expansion. SAIMEMORY will need significantly more capital to reach production.
Ecosystem compatibility: ZAM must interface with AI accelerator memory controllers designed for HBM. That requires either ecosystem collaboration or a proprietary stack — both are nontrivial.
Timeline pressure: Prototypes are targeted for FY2027, commercialization for FY2029. By then, HBM5 and potentially HBM4E will be shipping. ZAM enters a moving target.
Jim Handy from Objective Analysis put it plainly: “I wouldn’t call it vapor, but this is an awfully early announcement for something that’s not supposed to be in volume production until 2030.” That is fair commentary.
Outlook
The 2026 VLSI presentation was a meaningful step. ZAM moved from press releases and patents to a demonstrated nine-layer functional structure presented at one of the world’s top three semiconductor conferences. The addition of PSMC and AP Memory as collaborators expanded the paper consortium into something closer to a real supply chain.
If ZAM’s claimed 40–50% power reduction is validated at production scale, it could become a compelling alternative for inference-heavy workloads, especially as data center energy costs continue to rise. Intel’s own AI accelerators would be a natural first deployment vehicle. Custom memory controller integration with accelerator dies via UCIe or SerDes interfaces is also part of the long-term vision.
More importantly, ZAM is not just a technology bet. Seems like it is a coordinated effort by the US, Japan, and Taiwan to establish an alternative to the existing HBM supply chain. Whether the technology succeeds or not, the ecosystem around it — national laboratory involvement, government subsidies, diversified foundry access — signals a structural shift in how the world thinks about AI memory supply security.
Watch the 2027 prototype demonstrations closely. Those will tell us whether ZAM’s ambitious claims have legs.
If I have missed any ZAM developments or you have additional context to add, please comment below — I will update this article as things evolve.
