Welcome to Learn AI Infra — a curated space exploring the systems, silicon, and networks powering modern AI. From GPUs to data centers, dive into the infrastructure that makes intelligence possible.
Articles
Articles
Welcome to Learn AI Infra — a curated space exploring the systems, silicon, and networks powering modern AI. From GPUs to data centers, dive into the infrastructure that makes intelligence possible.
Few companies come up as often in AI infrastructure conversations as NVIDIA, and few product lines are as hard to hold in one’s head. In roughly eighteen months, the portfolio has grown from GPUs and a software library into a full stack: CPUs, rack-scale systems, scale-up and scale-out networking, DPUs, context-memory storage, reference designs for entire facilities, inference orchestration software, open models, and now an enterprise agent framework. In this article, I will walk through that portfolio layer by layer, as it stands in October 2026.
The AI Leadership Forum, managed by IT Brand Pulse, hosted the first episode of the Endless Memory with CXL® series on September 30, 2026. The speakers came from an analyst firm and companies actively involved in CXL implementations, and this first episode set the stage for the sessions to follow. This episode examined why AI needs so much memory, the supply and cost pressures around DRAM, and practical ways of closing the gap.
A GPU cluster with terabytes of pooled memory and blistering local bandwidth is only as good as the fabric that lets thousands of those GPUs exchange gradients, activations, and KV cache fragments with each other in microseconds. That fabric, for a large and growing share of AI training and inference clusters, runs on RDMA over Converged Ethernet version 2, or RoCE v2.
But an AI accelerator is only as useful as the software that lets it run a model, and for AMD's Instinct GPUs, ROCm is that software. If CUDA is the reason NVIDIA's hardware advantage has proven so durable, ROCm is AMD's answer to the same problem: how do you get PyTorch, vLLM, and a few hundred thousand developers to treat your silicon as a first-class citizen rather than an afterthought.
As port speeds climbed from 400G to 800G to 1.6T, the electrical trace between the switch ASIC and the front-panel optical module got harder to drive without burning power on retimers and losing signal to trace loss. Co-Packaged Optics, or CPO, attempts to move the optics off the front panel and onto the same package as the switch or compute die, so the electrical path nearly disappears.
This article examines why NVMe has become foundational to modern AI workloads, the technical developments driving its adoption, and the considerations organizations should weigh when architecting AI storage systems.
Recently, NVIDIA introduced a new architecture, called NVHBM, which pulls the memory controller out of the XPU chip and puts it inside the HBM stack's own base die. Amazon's Annapurna Labs is already on board for Trainium4.
On July 15, 2026, the Union Cabinet approved Semicon 2.0, the second phase of India's semiconductor policy, with a fiscal outlay of ₹1,27,500 crore (roughly $13.3 billion). While the numbers look good, I believe it’d be good to look at what Semicon 2.0 actually proposes, how it builds on its predecessor, and where there are gaps, still.