Co-Packaged Optics: Moving Light Closer to Silicon

Written By Dhupinder Malhotra

Every article in this series eventually runs into the same wall: the electrical link. CXL, SOCAMM, and HBF all wrestle with getting bits into and out of a package fast enough, cheaply enough, and without melting anything. This time, I want to talk about what happens outside the package, at the point where a switch or accelerator hands data off to the network, over copper traces to a pluggable transceiver sitting at the front panel.

That handoff is one of the more expensive parts of an AI data center. As port speeds climbed from 400G to 800G to 1.6T, the electrical trace between the switch ASIC and the front-panel optical module got harder to drive without burning power on retimers and losing signal to trace loss. Co-Packaged Optics, or CPO, attempts to move the optics off the front panel and onto the same package as the switch or compute die, so the electrical path nearly disappears.

This isn't a brand-new idea; Broadcom's Bailly shipped in 2024, and the concept goes back further still. But 2025 and 2026 turned CPO from a lab curiosity into shipping silicon from multiple vendors, backed by an actual interoperability standard. Let's get into it.

Why Now: The Pluggable Optics Power Wall

For two decades, pluggable transceivers, SFP, QSFP, and now OSFP modules did their job well. You plug a module into a front-panel cage, it talks to the switch ASIC over a short electrical trace, and if it fails, you swap it in minutes without touching anything else. That modularity is valuable, and it's a baseline against which CPO has to justify itself.

The trouble is what happens to that electrical trace as SerDes rates climb. At 800G and 1.6T port speeds, the electrical path from the ASIC to the front panel needs a DSP-based retimer inside the pluggable module just to recover a clean signal, and that retimer alone can account for a meaningful share of a transceiver's power draw. Multiply that across tens of thousands of ports in a large GPU cluster, and pluggable-optics power becomes a line item that data center operators can no longer treat as background noise.

AI clusters make this worse in a specific way. Training and inference workloads generate sustained, high-fanout east-west traffic between GPUs, not the bursty north-south patterns traditional networking was designed around. Every watt spent moving bits between accelerators is a watt not spent on compute, and every extra millisecond of tail latency from a flaky link can stall an entire training job. Thus, enormous east-west bandwidth, low tolerance for power waste, low tolerance for jitter, form the pressure that pushes optics closer to the die.

What Co-Packaged Optics Actually Changes

In a conventional design, light is converted to electricity (and back) at a pluggable module on the front panel, and that electrical signal then has to travel several inches of PCB trace to reach the switch ASIC, hence the need for retimers and the power they cost. CPO shortens that electrical path to millimeters by placing the photonic engine directly on the same substrate or package as the ASIC, right next to the silicon it is talking to.

The mechanics: a photonic integrated circuit converts the switch's electrical signals to light using components like ring modulators or Mach-Zehnder modulators, and that light exits the package through fiber shuffles or fiber-array units rather than through a stack of removable transceiver cages. Because the electrical hop is so short, the DSP that pluggables need for signal recovery can often be eliminated or simplified, which is where most of the power savings come from.

One design choice shows up across nearly every serious CPO product on the market: the laser itself usually stays off the package. Lasers are temperature-sensitive, they degrade faster than the surrounding electronics, and burying one inside a switch package means a single laser failure could force a full system pull. So vendors like NVIDIA, Broadcom, and the OIF standard alike, keep the light source in a separate, still-pluggable module, feeding light into the co-packaged photonic engine via fiber. It's a pragmatic compromise: you get the electrical-path savings of co-packaging without fully giving up the serviceability of a swappable component.


Who's Shipping What

A few CPO implementations are detailed below.

NVIDIA Quantum-X and Spectrum-X Photonics

NVIDIA announced its CPO switch line at GTC in March 2025, developed jointly with TSMC. The Quantum-X Photonics InfiniBand switch (the Q3450-LD) packs 144 ports of 800Gb/s for roughly 115 Tb/s of aggregate bandwidth, built around 200G SerDes and TSMC's 3D-stacked silicon photonics packaging. NVIDIA's own figures claim a 3.5x reduction in power consumption compared to pluggable optics and a drop in signal loss from roughly 22 dB to 4 dB.

Each switch uses external light sources, banks of continuous-wave DFB lasers that are physically separate from the co-packaged photonic engines, following the pattern above: keep the failure-prone, heat-sensitive part serviceable. InfiniBand CPO started shipping to early-access customers such as Lambda in the second half of 2025; the Ethernet-flavored Spectrum-X Photonics variant is slated for 2026. NVIDIA has been explicit that CPO is additive, not a replacement; pluggable-optics switch systems remain on the roadmap alongside it.

Broadcom Tomahawk 6 – Davisson

Broadcom has the longer track record here: Bailly, its first-generation CPO Ethernet switch, shipped in 2024 at 51.2 Tb/s. In October 2025, Broadcom began shipping Tomahawk 6 – Davisson (BCM78919), its third-generation CPO platform, doubling that to 102.4 Tb/s using sixteen 6.4 Tb/s optical engines built on TSMC's Compact Universal Photonic Engine (COUPE) process.

Broadcom quotes roughly 70% lower optical-interconnect power consumption versus pluggable alternatives, and, notably, Davisson keeps replaceable laser modules (RLMs), a serviceability choice that has been part of Broadcom's CPO line since Bailly. Broadcom frames the product around AI-specific traffic patterns: sustained east-west flows and low tolerance for link flaps, rather than the bursty, general-purpose traffic pluggable Ethernet was originally optimized for.

Ayar Labs: Optical I/O as a Chiplet

Ayar Labs takes a different angle on the same problem; instead of a co-packaged switch, it sells an optical I/O chiplet meant to sit inside someone else's package. Its TeraPHY chiplet, paired with the SuperNova external light source, became the industry's first UCIe-compliant optical chiplet in 2025, delivering 8 Tbps of bidirectional bandwidth over 16 wavelengths of light per port.

The UCIe compliance is of significance because it means TeraPHY is meant to plug into a multi-vendor chiplet ecosystem rather than lock a customer into one vendor's monolithic photonics stack, at least in principle, since real multi-vendor interoperability is still early. Ayar Labs positions this squarely at scale-up fabrics, the GPU-to-GPU links inside and across a rack, rather than at switch-to-switch networking.

Marvell / Celestial AI: Photonic Fabric

Marvell's $3.25 billion acquisition of Celestial AI, completed in February 2026, brought Photonic Fabric, a chiplet-based optical interconnect aimed initially at scale-up XPU-to-XPU links, into Marvell's portfolio. Celestial AI's first-generation chiplet supports 16 Tbps; a second generation targets 64 Tbps using the same optical channel count.

Marvell has also described a Photonic Fabric Memory Appliance that uses optical links to pool up to roughly 32 TB of DDR5 and about 1 TB of HBM across 16 hosts, described internally as a "photonic-CXL" approach where CXL handles the host-side protocol and optics solve the reach and bandwidth problem that pure electrical CXL fabrics run into at rack scale. It's a direct echo of the memory-pooling ambitions I covered in the CXL piece, just with light doing the heavy lifting instead of copper. Noteworthy, though, Marvell itself has said the newest performance targets are pre-silicon estimates, and working silicon is still ahead.

Standardization: The OIF Steps In

CPO's biggest structural risk is vendor lock-in, a switch and its optics coming from a single vendor, with no path to mix and match. The Optical Internetworking Forum (OIF) has been working on this since 2020, and its Co-Packaging Framework has produced two concrete implementation agreements: the 3.2Tb/s Co-Packaged Module IA (OIF-Co-Packaging-3.2T-Module-01.0, finalized in 2023), which defines a 3.2T module with 32 electrical lanes at 112G (or 56G in backward-compatible mode) and 8x400G optical interfaces for FR4 or DR4 connectivity, and the External Laser Small Form Factor Pluggable (ELSFP) IA, which standardizes exactly the kind of pluggable, replaceable laser module that NVIDIA, Broadcom, and others have converged on independently.

The standard is a common language for module-level interoperability, not a spec that today's shipping silicon strictly conforms to, Broadcom's Bailly and Davisson engines run at 6.4T, not the OIF's 3.2T reference module, and NVIDIA's designs are built around 200G SerDes rather than the OIF's 112G lanes. The OIF standard gives the industry a shared vocabulary and a socket concept that allows for rework and eventual field replacement, but actual multi-vendor plug-and-play CPO; swap a Broadcom optical engine into an NVIDIA switch package, is not something that exists today, and may not for a while.

COBO (the Consortium of On-Board Optics) has also stood up its own CPO working group, focused on openness standards for multi-vendor choice, and coordinates with both OIF and IEEE on the Ethernet side. The standards infrastructure exists; the market discipline to actually converge on it is still forming.

Where CPO Fits in an AI Fabric

CPO isn't spreading evenly across a data center, it is landing first at the densest, shortest, most homogeneous links: the scale-up tier that knits GPUs together within and across a rack, where bandwidth-per-rack is the binding constraint and the links are uniform enough that an operator can commit to a single vendor's optical engine. That's consistent with where Ayar Labs and Celestial AI/Marvell are aiming their chiplet-based optical I/O, and it's also where NVIDIA and Broadcom's CPO switches see their first hyperscale deployments, InfiniBand and Ethernet fabrics connecting large, homogeneous GPU pods.

Longer, more heterogeneous links like leaf-to-spine, campus interconnect, or anything crossing multiple vendors' equipment, are staying on pluggable optics (and increasingly linear-drive pluggable optics, LPO, which removes the DSP from a pluggable module without co-packaging it) for the foreseeable future. Pluggables remain the default everywhere operators need modularity, multi-vendor sourcing, or simple field service, which today is most of a data center.


Honest Caveats

CPO is real, shipping, and solving the power problem, but the industry's own numbers tell you it's still a small fraction of the market. By most 2026 estimates, CPO accounts for well under 1% of optical modules deployed in AI data centers, with projections putting it at roughly a third of the market by 2030. That's a long runway, not a fait accompli, and projections that must be considered directional rather than precise.

Serviceability is the recurring, unresolved concern, and I don't think the industry has fully answered it yet. In a pluggable world, a failed optical module is a five-minute swap. In a CPO world, if a non-laser component on the co-packaged engine fails, the failure domain can be the entire switch package, pulling out and replacing a multi-thousand-dollar system instead of a module. Vendors have mitigated the laser-specific version of this problem with external, pluggable light sources, but that doesn't cover every failure mode on the photonic engine itself, and hyperscalers at OCP reliability workshops have reportedly said CPO failure rates need to get below roughly 0.1 FIT before they're comfortable with the larger blast radius. Public, large-scale, long-term reliability data to prove that is still thin, most of what's cited is vendor lab data or early field trials at Broadcom and now NVIDIA volumes.

Vendor lock-in is a real commercial risk, not just a theoretical one. Despite the OIF's standardization work, the switch-plus-optics combination shipping today is effectively single-vendor: Broadcom's Davisson and NVIDIA's Quantum-X are each their own closed system from ASIC to photonic engine. A hyperscaler adopting CPO at scale today is making a bigger bet on one vendor's roadmap than it would with pluggable optics, where the transceiver market has real multi-vendor competition.

Cost is another place where the marketing gets ahead of the economics. At current volumes, CPO does not have a clear cost advantage over high-volume pluggable optics, the manufacturing yield challenges of co-packaging a photonic engine with a large switch ASIC (a defect in either die can force scrapping the whole assembly) work against it. The claimed power and density benefits are real and vendor-validated in several cases, but the specific savings percentages you'll see in press materials (3.5x, 70%, and similar figures) are vendor-reported comparisons against specific prior-generation baselines, not independently audited, apples-to-apples industry benchmarks. And market-size figures for CPO vary by a wide margin depending on the analyst firm.

Finally, most of what is shipping today is switch-side CPO for scale-up and scale-out networking. The chiplet-based optical I/O for direct XPU-to-XPU or XPU-to-memory links, Ayar Labs' TeraPHY, Marvell/Celestial AI's Photonic Fabric, is earlier stage, with the more ambitious claims (like the Photonic Fabric Memory Appliance) explicitly still pre-silicon as of this writing.

Outlook

The direction is clear even if the timeline is fuzzy: as port speeds push toward 3.2T and beyond, the electrical-path power penalty pluggables carry only gets worse, and CPO's value proposition strengthens correspondingly. Expect the near-term action to stay concentrated in scale-up fabrics inside AI pods, with switch-level CPO expanding gradually into scale-out networking as reliability data accumulates and the OIF's standards mature into something closer to real multi-vendor interoperability.

The more interesting long-term thread, to me, is the convergence with memory. Marvell's Photonic Fabric Memory Appliance and Panmnesia's CXL-over-fabric work (which I covered in the CXL article) are both circling the same idea from different directions: using optical links to make pooled, disaggregated memory practical at rack and multi-rack scale. If that convergence plays out, CPO stops being purely a networking story and becomes part of how AI infrastructure solves the memory wall too.

I might have missed implementations or standards updates. Please comment with anything I have overlooked; I'll add to this article.

References

Dhupinder Malhotra
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