Few companies come up as often in AI infrastructure conversations as NVIDIA, and few product lines are as hard to hold in one’s head. In roughly eighteen months, the portfolio has grown from GPUs and a software library into a full stack: CPUs, rack-scale systems, scale-up and scale-out networking, DPUs, context-memory storage, reference designs for entire facilities, inference orchestration software, open models, and now an enterprise agent framework.
In this article, I will walk through that portfolio layer by layer, as it stands in October 2026. The aim is a map and not a spec sheet: what each product is, where it is placed, and what problem it is meant to solve. I assume you are comfortable with terms such as HBM, NVLink, and KV cache.
A note on sources: nearly every performance number below is an NVIDIA claim, usually measured on workloads and numeric precisions that NVIDIA chose. I flag this where it matters, and I collect the critical points in a separate section near the end.
The Portfolio at a Glance
NVIDIA frames everything around the AI factory: a data center that takes in data and power and produces tokens. Each product in the portfolio is designed as one component of that factory, which is why the company now talks about racks, pods, and even whole facilities rather than chips.
Data Center Compute
Blackwell and Blackwell Ultra
The current volume platform is Blackwell Ultra in the GB300 NVL72 rack: 72 Blackwell Ultra GPUs and 36 Arm-based Grace CPUs in one fully liquid-cooled system. NVIDIA says it delivers 1.5x the dense FP4 compute and 2x the attention performance of standard Blackwell, with 288 GB of HBM3e per GPU and 800 Gb/s of ConnectX-8 networking per GPU.
NVIDIA’s claim is up to 50x higher AI factory output than Hopper for reasoning inference. This figure comes from one specific configuration (DeepSeek-R1, with FP4 and Dynamo disaggregated serving on GB300 against FP8 in-flight batching on H100), so treat it as a best case. In the same comparison, NVIDIA cites a 10x gain in per-user responsiveness and 5x higher throughput per megawatt.
On the training side, GB300 NVL72 debuted in MLPerf Training v5.1, where NVIDIA reported the first use of FP4 (its own NVFP4 format) in that benchmark while meeting the accuracy requirements.
Vera Rubin: Six Chips, Then Seven
The next generation was launched at CES in January 2026 as a platform and not a GPU: extreme co-design across six chips, namely the Vera CPU, Rubin GPU, NVLink 6 switch, ConnectX-9 SuperNIC, BlueField-4 DPU, and Spectrum-6 Ethernet switch. At GTC in March 2026, NVIDIA added a seventh, the Groq 3 LPU, which I cover below.
Rubin GPU: two reticle-sized dies, 288 GB of HBM4, and up to 22 TB/s of memory bandwidth per GPU. NVIDIA quotes up to 50 PFLOPS of FP4 per GPU.
Vera Rubin NVL72: 72 Rubin GPUs and 36 Vera CPUs in one NVLink 6 domain, with 3.6 TB/s per GPU and 260 TB/s per rack.
Rack-level figures (NVIDIA): 3.6 exaFLOPS of NVFP4 inference, 2.5 exaFLOPS of NVFP4 training, 20.7 TB of HBM4, and 54 TB of LPDDR5X attached to the Vera CPUs.
Serviceability: the rack is 100% liquid-cooled and described as fanless, tubeless, and cableless, with a second-generation RAS engine and what NVIDIA calls the first rack-scale confidential computing platform.
HGX Rubin NVL8: an eight-GPU server board for customers who want x86-based servers instead of the rack-scale design.
NVIDIA claims up to 10x lower cost per token and 4x fewer GPUs to train mixture-of-experts models compared with Blackwell. As on every vendor slide, the baseline and the workload decide how far these numbers travel.
Status: per NVIDIA’s May 2026 announcement, production shipments of Vera Rubin were set to begin “this fall.” Supermicro announced on September 23 that it had started shipping Vera Rubin NVL72 racks, though it disclosed no volumes or customers. Reports citing NVIDIA say initial shipments came in the third quarter, with a volume ramp in the fourth.
Rubin CPX and Groq 3 LPX: Specialised Inference Silicon
LLM inference has two phases with very different needs. Prefill reads the whole prompt and is compute-bound. Decode produces output one token at a time and is limited by memory bandwidth. NVIDIA’s response is to stop treating them as one job.
In September 2025, it announced Rubin CPX, a monolithic-die GPU with 128 GB of GDDR7 and on-chip video encode and decode, aimed at million-token context workloads such as coding assistants and generative video. It was slated for the end of 2026. The May 2026 production announcement does not mention it, and at GTC 2026 the emphasis moved to a different part. I could not find NVIDIA confirming the CPX’s current status, so I treat it as unclear.
That different part is the Groq 3 LPU, built from technology NVIDIA obtained from Groq in a deal reported at around US$20 billion and described by The Register as an acquihire. An LPU keeps its working memory in on-chip SRAM, which gives very high bandwidth (about 150 TB/s per chip, against 22 TB/s of HBM4 on Rubin) but very little capacity.
The Groq 3 LPX rack holds 256 LPUs, each with 500 MB of SRAM, for 128 GB in aggregate and 40 PB/s of SRAM bandwidth. Deployed beside a Vera Rubin NVL72, the LPUs handle the latency-sensitive feed-forward and mixture-of-experts layers of decode, while Rubin GPUs continue to handle prefill and decode attention. NVIDIA claims the pairing generates 35x more tokens than Vera Rubin NVL72 alone on a 1-trillion-parameter model with a 400k context window, at a cost it puts at US$45 per million tokens. Sources differ on whether the 35x is framed per megawatt, so I quote it as a throughput claim. The pitch to inference providers is a premium, low-latency tier of tokens.
Vera: The CPU Goes Standalone
Vera is NVIDIA’s custom Arm CPU: 88 Olympus cores with spatial multithreading (176 threads) and LPDDR5X memory, linked to Rubin GPUs over 1.8 TB/s NVLink-C2C. What changed in 2026 is that NVIDIA also sells it on its own. The reasoning is that agentic AI and reinforcement learning need a great deal of CPU-side work: sandboxes, tool calls, code execution, and orchestration.
NVIDIA’s Vera rack integrates 256 liquid-cooled CPUs and is said to sustain more than 22,500 concurrent CPU environments. NVIDIA claims up to 1.8x the speed of leading x86 CPUs on agentic workloads (1.9x for Python, 1.7x for compilation and code analysis), measured on its own benchmarks with preliminary specifications. Named collaborators include Alibaba, ByteDance, Meta, Oracle Cloud Infrastructure, CoreWeave, Lambda, Nebius, and Nscale, and 18 system makers, among them Dell, HPE, Lenovo, and Supermicro, are listed as partners.
Roadmap: Rubin Ultra, Kyber, and Feynman
NVIDIA now publishes its roadmap years ahead, because, as Jensen Huang put it, data center land and power have to be planned two to three years out. Rubin Ultra is announced for the second half of 2027 with four compute chiplets and 1 TB of HBM4E, in a new liquid-cooled Kyber rack that Huang said would draw around 600 kW. Feynman follows in 2028, with die stacking, custom HBM, a new Rosa CPU, the LP40 LPU, BlueField-5, and ConnectX-10.
Two cautions. The rack naming has shifted: Rubin Ultra was first shown as NVL576 and later described as a Kyber NVL144 configuration under a changed counting scheme. And a SemiAnalysis report, relayed by Techzine, says Kyber may slip to 2028 because of a difficult 78-layer midplane board. NVIDIA has not confirmed that.
Networking, Interconnect, and Storage
Adding GPUs helps only if the fabric keeps up, so NVIDIA sells networks for three distances: scale-up inside a rack, scale-out across racks, and scale-across between data centers
NVLink Fusion (announced May 2025) is NVIDIA’s attempt to keep its fabric central even when customers want custom silicon. MediaTek, Marvell, Alchip, Astera Labs, Synopsys, and Cadence joined for custom accelerators, and Fujitsu and Qualcomm for CPUs, with Arm, Intel, and SiFive later announcing CPU-side support. As analysts noted at launch, a Fusion design still needs some NVIDIA silicon in it.
On Ethernet, Meta and Oracle announced in October 2025 that they would standardize on Spectrum-X switches. Meta is integrating them into its FBOSS software platform. NVIDIA’s co-packaged optics switches integrate silicon photonics into the switch package and claim 3.5x better power efficiency and 10x better resilience than traditional pluggable optics. In May 2026, NVIDIA said Spectrum-X Ethernet Photonics was in production, with CoreWeave, Lambda, and Oracle Cloud Infrastructure as first adopters.
BlueField-4 also anchors the Inference Context Memory Storage platform, a pod-level tier for KV cache. As context windows and agent sessions grow, KV cache outgrows GPU memory and local storage, and general-purpose enterprise storage adds overheads that stall GPUs. NVIDIA’s answer is a purpose-built layer in between, and storage vendors such as WEKA and VAST Data are building to it.
From Chips to Facilities: DGX, MGX, and AI Factory Design
NVIDIA’s reference building blocks are layered. MGX is a modular rack architecture supported by around 80 ecosystem partners, and the LPX and Vera CPU racks are built on it. A DGX SuperPOD of Vera Rubin consists of eight NVL72 racks connected by Spectrum-6 switches with co-packaged optics.
Above the rack, the Vera Rubin DSX AI Factory reference design and the Omniverse DSX Blueprint target gigawatt-scale facilities. The blueprint is an OpenUSD-based digital twin used to model layouts, power, and cooling before construction, and later as an operating tool. Partners include Schneider Electric, Siemens, Vertiv, Eaton, Cadence, and Dassault Systèmes. On the operations side, Mission Control is the software that orchestrates workloads across the NVLink domain and integrates with facility systems.
Desktop, Workstation, and Edge
The same software stack runs down to a desk or a robot. NVIDIA positions this tier for developers who want to prototype locally before moving to a data center, and for robots and machines that must run models on board.
One thing to avoid: comparing DGX Spark and Jetson Thor on the headline numbers alone. Thor’s 2,070 TFLOPS and Spark’s 1 PFLOP are both sparse FP4, but community tests show the two parts have quite different architectures, with different SM counts and tensor-core features, so real performance depends on the workload.
The Software Platform
If the hardware is the visible part of NVIDIA, the software is the part that keeps customers on it. The foundation is CUDA, which turned 20 this year, and above it sit the CUDA-X libraries. NVIDIA counts more than 400 of them, including cuDNN for neural network primitives, NCCL for multi-GPU communication, TensorRT and TensorRT-LLM for inference, CUTLASS for kernels, and RAPIDS (cuDF, cuML, cuGraph) for data science.
Dynamo 1.0 (March 2026): open-source inference orchestration that NVIDIA calls an operating system for AI factories. It sits above engines such as vLLM, SGLang, and TensorRT-LLM and integrates with LangChain, llm-d, and LMCache. It handles disaggregated prefill and decode, KV-aware routing, and scheduling. NVIDIA claims up to 7x better inference performance on Blackwell.
NIM microservices: prepackaged inference containers for deployment on any GPU environment. NIM is gaining Dynamo capabilities over time.
NeMo: the framework family for building, customizing, and guarding models and agents.
AI Enterprise: the licensed, supported distribution. The Dynamo enterprise containers are free to use, but commercial support requires an AI Enterprise subscription.
NemoClaw (GTC 2026): an open-source stack that installs the OpenClaw agent platform with NVIDIA’s Nemotron models and the OpenShell sandbox runtime in one command, adding privacy and security controls to autonomous agents.
Models and Physical AI
NVIDIA also publishes open models, which is unusual for a hardware vendor. The Nemotron 3 family, first released in December 2025, uses a hybrid Mamba-Transformer mixture-of-experts design. It spans Nano (30B parameters, about 3B active), Super (120B, about 12B active), and Ultra, which has 550B parameters (about 55B active) and a 1M-token context window, plus Omni and VoiceChat variants announced at GTC 2026. NVIDIA describes the family as permissively licensed, with public training data and pipelines.
For physical AI, the Cosmos world foundation models (Predict, Transfer, Reason) generate synthetic video and reason about the physical world, and Isaac GR00T is the robot foundation model line for humanoids, with N1.7 current and N2 previewed. Alpamayo targets autonomous driving, and Clara covers healthcare and life sciences. At GTC 2026, NVIDIA said Uber would launch a fleet running NVIDIA’s DRIVE AV software in 28 cities by 2028.
My view is that open models serve a commercial purpose: they create demand for NVIDIA hardware and make it harder for any single closed model vendor to dictate the stack. That is an interpretation, not an NVIDIA statement.
Caveats
A portfolio this broad deserves a critical read. These are the points I would keep in mind.
Vendor-reported numbers. Almost every figure above is NVIDIA’s, measured on chosen workloads. Many compare FP4 on new hardware with FP8 on old, or use sparse figures. The 50x claim for GB300 is for one DeepSeek-R1 configuration.
Inconsistent multipliers. At GTC 2025, the 3.6 exaFLOPS NVL144 figure was presented as 3.3x GB300 NVL72. At CES 2026, the same 3.6 exaFLOPS NVL72 figure was presented as 5x the prior generation. Rubin’s HBM bandwidth also moved from 13 TB/s to 22 TB/s, and the rack name changed from NVL144 to NVL72. I use the latest figures, but the sources do not reconcile the baselines.
Status ambiguity. “Full production” was announced in January, again in May as “ramping,” with shipments set for the fall, and one integrator has now announced shipping. That is progress, but it is not evidence of volume. The status of Rubin CPX is unclear, and the Kyber delay report is unconfirmed.
The LPU is a new programming target. NVIDIA says CUDA is unchanged and the LPU works as an accelerator alongside the CUDA-running Vera Rubin rack, so it is not a CUDA-native chip. SRAM capacity is small (128 GB per rack), so LPX suits decode-heavy, latency-sensitive tiers and is not a general replacement for GPUs.
Lock-in is a design goal. CUDA, NVLink, NVFP4, and the DPU and storage layers reinforce one another. Dynamo is open source, and Spectrum-X is standards-based Ethernet, which helps. But NVLink Fusion still needs NVIDIA silicon, and the best results are claimed on NVIDIA’s full stack.
Benchmarks. NVIDIA says it was the only platform to submit results on every MLPerf Training v5.1 test. That shows breadth, but it is not proof of superiority on each test, and some rivals did submit on some tests.
Power and facilities. Racks are fully liquid-cooled, and Kyber is planned at about 600 kW. Operators need power, cooling, and land years ahead, and Huang’s own US$1 trillion order outlook through 2027 is a management projection, not a reported backlog.
Edge figures. Sparse FP4 TFLOPS flatter the numbers on desktop and edge parts, and the DGX Station and Spark come in various OEM versions with different pricing and availability.
Outlook
NVIDIA reported record revenue of US$81.6 billion for its first fiscal quarter of 2027, with data center revenue of US$75.2 billion, up 92% year over year. The company has committed to an annual platform cadence, with Vera Rubin ramping now, Rubin Ultra planned for 2027, and Feynman for 2028.
The more interesting shift is where NVIDIA is spending its effort: heterogeneous racks (GPU, LPU, CPU), context-memory storage, orchestration software, and facility design. It is moving from selling the fastest chip to selling the whole token factory. Whether customers accept that, or mix in custom silicon through NVLink Fusion and open Ethernet, will be the story to watch.
Final Words
This is a fast-moving portfolio, and I have surely missed products and details. Please comment to point out anything I got wrong or left out; I’ll update the article.
