CXL is Alive and Kicking!
In the past, many subtle requiem-like pronouncements on the future of CXL as an interconnect of choice had left companies wondering whether to go ahead with their investments in CXL implementations. Some continued while being wary, some have held back. But the recent developments in the CXL world have given companies and CXL enthusiasts reasons to be upbeat about this interesting technical standard for implementing memory expanders, fabrics to implement memory pooling and sharing, and yes, accelerators, too.
In this article, I will talk about some of the recent CXL implementations, most of them geared to serve the insatiable appetite of AI compute infrastructure. But before that, a few introductory lines on what drives CXL and what is the unique selling proposition (USP) for CXL. Here, I assume that you are aware of the protocol stack (CXL.io, CXL.mem, and CXL.cache) that constitutes CXL. Also, the three device types that exist by implementing a combination of these protocols while keeping (PCIe-like) CXL.io as a must-implement protocol.
Undeniably, memory expansion has been the most popular function of CXL. But the implementers have found room for innovation even in this function, as we will see later in the article.
Drivers for CXL
It’s the agentic AI era. AI agents demand huge amount of memory. KV cache sharing and vector database indexing has an enormous appetite for fast memory.
When we talk about memory as a pillar of an AI data center (compute, network, and storage being the other pillars), we are more concerned about these four aspects of memory:
Bandwidth
Latency
Capacity
Cost
Traditional DRAMs that constitute the system memory fare well on the bandwidth and latency aspects. But capacity becomes a concern; it is difficult to accommodate swathes of memory; also, memory chips are expensive. And not to talk about the memory shortages that the industry is globally dealing with.
SSDs as an alternative or even an accompaniment cannot directly bridge the gap; it is either impossible or needs careful thinking and implementation for SSDs to bridge the gap. SSDs can provide capacity but do badly on the latency part.
So, we need something like DRAM to avoid memory stalls, idle state of GPUs, lower tokens/sec, and higher power consumption per token.
What has CXL enabled?
CXL attempts to address the wild requirements of the AI world by providing huge amounts of memory at comparable bandwidths, all behind the PCIe interface.
CXL introduces the concept of memory pooling, in which case, multiple hosts can access a pool of memory (running into terabytes) attached to multiple devices via PCIe interface. This ensures that there aren’t situations in which one processing element is sitting idle with its memory while another busy processor is starving and unable to satisfy its memory requirements.
Another feature supported by CXL is memory sharing, in which case same physical memory regions can be shared between and concurrently accessed between multiple independent hosts, thus avoiding data duplication and movement.
These techniques further lead to the decupling between processing elements and memory installations, giving birth to disaggregated structures that results in more scalability and shareability. This ensures optimum utilization of processing elements like GPUs for servicing AI workloads.
Now let’s talk about latency. Latency, as compared to directly-attached DRAM, is a concern in traditional CXL implementations; however:
Techniques like memory sharing dramatically reduce latency.
The latency can be absorbed by less frequently accessed “cold” data.
Another “welcome” benefit of CXL is that the memory that is used for expansion can be DDR4 memory; this reduces e-waste and leads to better utilization in the face of memory shortages.
Microsoft predicts that CXL memory pooling could trim server costs by 5% by lowering total memory needs by about 10%.
Outlook on CXL Market
According to Yole Group, CXL market will see a rise from US$2.1 billion in 2026 to US$16 billion by 2028.
A few CXL implementations
Now comes the interesting part. How does CXL physically show up in the world of data centers?
Note: Here we talk about memory expansion related implementations only.
We see a wide variety of physical implementations of CXL. The most popular and perhaps the least complex to implement are the memory expanders or the Type 3 devices. These essentially have a PCIe interface to the CPU and have provision to attach DRAM modules to provide that additional memory.
Then there are processors like the Intel Sapphire Rapids and Granite Rapids that support CXL as hosts. Some of the AMD servers too.
Staying loyal to the PCIe architecture of a root complex (host) and an end point (device) is a requirement; however, when we talk about memory pooling and sharing there is also a requirement for the middleware and infrastructure software elements, for, say, hosts running different operating systems. Implementation efforts are also required for switching, controller design, and paths that operate in the real world deployments.
This section details some of the recent CXL implementations and deployments planned for future that dramatically change the narrative of the feasibility of making use of CXL in the modern times AI infrastructure.
Panmnesia’s (CXL-based) AI Datacenter Infrastructure
Panmnesia is a South Korea based fabless company developing link solutions for AI infrastructure. They have developed a silicon-proven CXL controller and Port-Based Routing (PBR) switch for memory-centric fabrics. Both the controller and the switch are compatible with PCIe v6.4 and CXL v3.2. The USP:
Support for PCIe and CXL on a single die; this enables connectivity across a wide range of devices including PCIe-based GPUs, PCIe switches, CXL-compatible CPUs, CXL memory expanders, and CXL-based AI accelerators.
First to implement CXL Port-Based Routing
Port-based routing and Hierarchy-based routing (HBR) are implemented on a single chip. Introduced in CXL 3.x, PBR enables switches and devices to be connected in any topology; peer devices under a switch can communicate and exchange data with each other without going via host. Thus, data transfer paths are shortened and system performance is improved.Provides infrastructure to pool and independently manage (at the same time) diverse set of resources at the rack scale. This minimizes waste and underutilization. Additionally, large rack-scale fabrics can be created by chaining switches and devices.
Panmnesia has also proposed an AI data center architecture using CXL-based memory pooling in which the large KV Cache is stored and managed. Good news for agentic AI workloads.
New (CXL-based) Architecture for AI Datacenters
Panmnesia and SK Telecom, South Korea’s largest telco and a leading AI company, signed a strategic partnership at MWC26 in Barcelona to collaborate on developing a CXL-based next-gen AI datacenter architecture.
The proposed architecture aims to move beyond the monolithic server architecture and introduce a disaggregated architecture in which the CPUs, GPUs, and memory are interconnected at the rack level through Panmnesia’s CXL Fabric Switch. The resources required for each AI workload will be dynamically allocated thereby reducing inefficiencies arising out of underutilized and overburdened resources, resulting in cost benefits.
The second strategy is to replace traditional network-based interconnects with CXL resulting in improved computational efficiency. Panmnesia’s Link Controller will be leveraged to achieve this objective.
The two companies plan to validate the proposed architecture by running AI models and a comprehensive evaluation of GPU and memory utilization, latency, and throughput.
PoC deployments and commercialization will follow.
Samsung’s CXL-based Innovations
In April 2026, Samsung showcased its three CXL-related innovative techniques in a CXL Consortium webinar. These techniques detailed in respective IEEE papers are briefed below:
S-CHMU (CXL Hotness Monitoring Unit) – This is a hardware-assisted technique for managing the data placement between the local DRAM and CXL-attached memory tiers leading to greater efficiency gains.
CXL-PNM (CXL Processing Near Memory) – This is a technique for offloading data-intensive operations directly to the memory device, significantly reducing data movement and maximizing effective bandwidth.
Pangaea V2 (CXL Memory Orchestrator for K8s) - To make CXL viable in production, it must be cloud-native. Pangaea V2 is an advanced orchestrator that abstracts CXL resources for Kubernetes, allowing for dynamic, transparent allocation of expanded memory pools across containerized workloads.
Penguin’s (CXL-based) KV Cache Server
Penguin Solutions introduced the industry’s first CXL-based KV cache server called the MemoryAI™ KV cache server, which delivers up to 11 TB of memory (3TB of DDR5 main memory and up to 1 TB CXL Add-In Cards) to boost performance and efficiency in tackling enterprise-scale AI workloads. This server offers lower latency, higher throughput, increased efficiency of GPU clusters, and faster time-to-first-token. (TTFT)
The solution is compatible with NVIDIA Dynamo, NVIDIA’s software architecture for KV cache memory offloading.
Liqid’s Memory Pooling Solution
Liqid’s memory pooling solution disaggregates memory from the server and scales pools to 10-100 TB, thereby satiating the appetite of GPUs in terms of capacity and bandwidth. The solution boasts of no requirement for application rewrites.
The business benefits include lower cost per token because of more tokens per second.
Marvell’s Complete CXL Portfolio
Marvell has announced Structera S 30260, which succeeds the Apollo line of switches developed by XConn Technologies, a company that Marvell acquired. Structera S is a 260-lane CXL switch device that enables memory pooling at the rack level. If you combine this with Structera A near-memory accelerators, Structera X memory-expansion controllers, and Alaska P PCIe/CXL retimers, Structera X enables systems to take advantage of increased memory bandwidth and capacity via access to disaggregated memory resources outside the server.
Marvell is the industry’s first company with a CXL portfolio that spans all three CXL product categories: memory expansion, memory acceleration, and memory pooling.
Montage Technology’s Demonstration of DCD
Recently, Montage Technology successfully demonstrated a fully functional CXL Dynamic Capacity Device (DCD) system with their CXL 3.2 x8 memory expansion controller chip, showcasing how DCD technology with Multi-Head Device (MHD) support enables memory pooling and sharing across multiple hosts.
Intel’s Flat Memory Mode
Intel’s Flat Memory Mode (FMM), a feature of the Intel® Xeon ® 6 processors offers a hardware-based memory tiering technique for CXL Type 3 enabled systems. This mode offers a two-tier solution with one tier being the locally attached DRAM (Near Memory) and the second tier being CXL attached memory (Far Memory). In this mode, it is the hardware that handles the placement of data in each tier with no software involvement. The software sees the total capacity of the Near Memory and Far Memory. This techniques has been demonstrated to deliver dramatic throughput and latency benefits in experiments involving in-memory database workloads.
Xcena’s (CXL-based) KV Cache Storage Engine
Xcena proposed use of CXL for KV cache using a CXL Type 3 memory expander. They benchmarked their KV Cache storage engine against LMCache’s P2P backend, which makes use of TCP-based transfer. Maru, Xcena’s KV Cache storage engine built on CXL shared memory, as against the traditional practice of KV Cache sharing of copies of data across the network, writes the data to CXL memory once and it stays there. Only metadata (keys and location information) travels between the components. By enabling “zero-copy” KV cache sharing through CXL shared memory, they demonstrated up to 3.9x lower time to first token. (TTFT)
SK hynix
SK hynix introduced its first CXL memory module in 2022; and then a CXL 2.0-compliant product in 2023. Building upon its experience of developing CXL-based memory modules, SK hynix displayed its CMM-DDR5 products at the HPE Discover event. These included its first-generation, CXL 2.0-compatible, 128 GB module and a second-generation CXL 3.2-compatible, 256 GB module. At the event, the company also displayed a pooled memory server from Liqid with its CMM-DDR5 modules fitted.
Micron
Micron, another big memory player joined the race with its own CXL memory module unveiled in 2024.
CXL Adopters: Google & NVIDIA
According to sources, Google has started deploying CXL technology in its data centers. Reportedly, Google is installing CXL controllers to manage data flow between server CPUs and huge external memory pools.
In addition to PCIe 6, NVIDIA’s Vera CPU supports CXL v3.1 connectivity.
Final Words
CXL support is spreading across the stack.
I might have missed many CXL stories. Please comment to mention any that I have missed; I’ll add on to the growing list in this article.
