UALink vs NVLink: Can the Industry Out-Link Nvidia?

Written By Dhupinder Malhotra

If you've been following this series, you know I've been mapping the plumbing of AI infrastructure - CXL for memory expansion and pooling, SOCAMM for compact, socketed memory, High Bandwidth Flash for the tier below HBM, and, more recently, Ethernet-based approaches like ESUN. Today I want to zoom in on one specific, and frankly unavoidable, piece of that puzzle: UALink, and how it stacks up against the interconnect it was explicitly created to challenge — Nvidia's NVLink.

If CXL is about giving accelerators more memory, UALink is about letting hundreds of accelerators behave like one giant accelerator. That distinction matters, so let's start there.

Why Scale-Up Needs Its Own Interconnect

Modern AI training and inference don't run on a single GPU. A large model is sliced across dozens or hundreds of accelerators, and during every forward and backward pass, those accelerators are constantly exchanging activations, gradients, and KV cache fragments with each other. This is “scale-up”: tight, rack-level, all-to-all communication among accelerators sitting close together, as opposed to “scale-out,” the longer-haul networking that stitches racks and pods together across a data center.

Scale-up traffic has a different personality than ordinary data center traffic. It demands very low latency, very high bandwidth, and memory-semantic operations, such as loads, stores, and atomics, not just packet delivery. General-purpose Ethernet or InfiniBand, built for scale-out, were never optimized for this job. Nvidia solved it for its own GPUs a decade ago with NVLink, a proprietary interconnect. Everyone else, the AMDs, Intels, and hyperscalers of the world building their own custom silicon needed an open alternative so they wouldn't be permanently tied to Nvidia's fabric. That's the reason UALink exists.

What Is UALink?

The Ultra Accelerator Link Consortium was incorporated in October 2024, backed by a board that reads like a who's-who of the industry: AMD, AWS, Cisco, Google, HPE, Intel, Meta, and Microsoft at inception, with Alibaba Cloud, Apple, and Synopsys joining the board later. Broadcom was an early board member too, though (and I'll come back to this in the caveats section) it has since stepped away from the board.

UALink defines an open, memory-semantic, scale-up interconnect that allows accelerators to perform load, store, and atomic operations across the fabric, not merely send messages to each other. The consortium published its first specification, UALink 200G 1.0, in April 2025, defining 200Gbps throughput per lane, linking up to 1,024 accelerators per pod. The physical layer borrows from familiar Ethernet building blocks; the UALink PHY is based on 802.3 Ethernet PHY, defined for one, two, or four serial lanes running at a serial rate of 212.5G, which was a deliberate choice to piggyback on a mature, well-understood signaling ecosystem rather than inventing something from scratch.

The consortium hasn't stood still since that first release. In April 2026, it published four additional specifications defining In-Network Compute, Chiplet Definition, Manageability, and a standalone 200G Data Link and Physical Layer 2.0. The in-network compute piece is particularly interesting for practitioners; it moves some computation and reduction work into the fabric itself, reducing latency, saving bandwidth, and improving scaling efficiency for distributed training and inference. Splitting the physical layer specification out on its own was also a smart structural move: it lets the electrical and signaling layer iterate at its own pace - new speeds, new SerDes generations, without forcing a rewrite of the rest of the protocol stack every time.

UALink vs NVLink: The Real Comparison

Here's where it gets interesting for anyone deciding what to build on.

NVLink is now in its fifth production generation and heading into its sixth. NVLink 5.0, shipping with Blackwell (GB200/GB300), delivers 1,800 GB/s per GPU via 18 links at 100 GB/s each, and the GB200 NVL72 rack aggregates 130 TB/s of system bandwidth, supporting up to 576 GPUs in a non-blocking compute fabric. Nvidia isn't waiting around either. NVLink 6, arriving with the Rubin platform, enables 3.6 TB/s of bandwidth per GPU, and the Vera Rubin NVL72 rack connects 72 GPUs in an all-to-all topology for a total of 260 TB/s.

UALink's headline number, by contrast, is 200 Gbps (25 GB/s) per lane, scaling up via multiple lanes, with a pod ceiling of 1,024 accelerators, nearly double NVLink's per-rack GPU count, but at meaningfully lower per-link bandwidth today. In raw per-GPU throughput, NVLink currently has a clear lead; it's a mature, purpose-built, tightly integrated fabric that Nvidia controls end to end, from the GPU die to the switch silicon.

So why would anyone choose UALink?

Openness and choice. NVLink locks you into Nvidia's roadmap and, historically, Nvidia's silicon. UALink is a multi-vendor specification: any accelerator vendor, any switch vendor, any retimer vendor can build to the same open spec, the way the industry rallied around PCIe instead of a dozen proprietary bus standards. For hyperscalers building custom ASICs, or for AMD competing head-on with Nvidia's Instinct line, that vendor independence is the entire point, even if it means trading away some near-term bandwidth.

It's worth noting Nvidia hasn't ignored this pressure. With NVLink Fusion, launched at Computex 2025, Nvidia opened parts of NVLink to third-party CPUs and custom silicon, signing up partners like MediaTek, Marvell, Astera Labs, Fujitsu, Qualcomm, Arm licensees, and, more recently, Samsung Foundry and SiFive. It's a hedge: rather than cede the open-standard territory entirely to UALink, Nvidia is offering a controlled, licensed form of openness that still keeps NVLink at the center of the fabric.

Ecosystem and Early Silicon

On paper, UALink has broad backing. More than 65 members have signed on, and switch and retimer silicon is emerging from Astera Labs, Marvell, and others.

AMD is the most consequential early adopter. Its Helios rack-scale platform, detailed at Advancing AI events through 2026, is UALink's flagship proof point. But even here, the honest picture is nuanced: AMD's initial Helios and MI400-series systems aren't running native UALink silicon at all. They're running what AMD calls UALink-over-Ethernet (UALoE), effectively AMD's existing Infinity Fabric-over-Ethernet, rebranded and aligned to the UALink protocol layer, riding on Broadcom's Tomahawk 6 Ethernet switches. Astera Labs' own CEO has confirmed that true UALink-based switching silicon won't ramp until 2027, not 2026. So the first wave of “UALink” deployments in the field are, strictly speaking, a bridge - real UALink protocol semantics, but carried over Ethernet plumbing rather than purpose-built UALink switches.

Honest Caveats

In the spirit of this series, let's not gloss over the rough edges.

First, the Broadcom question. Broadcom was a founding UALink board member and was expected to deliver a UALink switch, but it has since stepped back from the consortium's board and redirected its energy toward its own Scale-Up Ethernet (SUE) framework, essentially betting that Ethernet, refined for scale-up latency and header efficiency, will get to market faster than purpose-built UALink switches. That's not a fatal blow to UALink, but it is a signal that even founding members see credible alternatives worth hedging toward, and it's part of why AMD's own first-generation systems lean on Ethernet rather than native UALink hardware.

Second, timing. Native UALink silicon, real switches, not Ethernet-tunneled workarounds,  realistically arrives in the 2026–2027 window, by which point NVLink 6 and Rubin will already be shipping at scale. UALink isn't catching a stationary target.

Third, bandwidth parity is still theoretical. Even the newest UALink specifications don't yet publicly demonstrate per-GPU bandwidth competitive with NVLink 5, let alone NVLink 6. The consortium's In-Network Compute and higher-speed physical layer additions are steps toward closing that gap, but they're specifications, not shipping silicon.

None of this means UALink is losing. It means the “open vs proprietary” contest in scale-up interconnects is still being fought on two fronts at once - UALink native silicon versus UALink-over-Ethernet versus NVLink Fusion's controlled openness; and it will likely take another product cycle or two before we know which combination hyperscalers standardize on.

Outlook

My honest read: UALink won't dethrone NVLink's raw performance lead in the near term, and it doesn't need to. Its value proposition isn't “faster than NVLink”; it's “not owned by Nvidia.” For hyperscalers and accelerator vendors who need a credible, multi-vendor path to rack-scale AI systems, that alone is worth building toward, even while leaning on Ethernet as a bridge in the interim. Whether UALink ultimately converges with efforts like ESUN, coexists alongside NVLink Fusion, or ends up as one of several open options is still an open question, and one I'll keep tracking in this series.

As always, if I've missed a UALink development, a vendor, or a nuance worth adding, let me know in the comments; I'll fold it in.

References

Dhupinder Malhotra
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