Welcome to Learn AI Infra — a curated space exploring the systems, silicon, and networks powering modern AI. From GPUs to data centers, dive into the infrastructure that makes intelligence possible.
Articles
Articles
Welcome to Learn AI Infra — a curated space exploring the systems, silicon, and networks powering modern AI. From GPUs to data centers, dive into the infrastructure that makes intelligence possible.
Recently, NVIDIA introduced a new architecture, called NVHBM, which pulls the memory controller out of the XPU chip and puts it inside the HBM stack's own base die. Amazon's Annapurna Labs is already on board for Trainium4.
On July 15, 2026, the Union Cabinet approved Semicon 2.0, the second phase of India's semiconductor policy, with a fiscal outlay of ₹1,27,500 crore (roughly $13.3 billion). While the numbers look good, I believe it’d be good to look at what Semicon 2.0 actually proposes, how it builds on its predecessor, and where there are gaps, still.
If compute is the engine of AI infrastructure, the network is the nervous system. It's time to turn to the two standards that carry data between servers and racks: InfiniBand and Ethernet.
In mid-July 2026, a Beijing-based startup most people outside AI circles had never heard of released what it calls the largest “open-weight” AI model in the world, meaning the trained model itself, not just access to it through an app or API, is available for anyone to download and run, and for a few days it became the biggest story in the industry.
HBM4 is JEDEC's answer, standardized as JESD270-4 in April 2025 with input from AMD, Nvidia, Google, SK hynix, Samsung, Micron, and other major players. It roughly doubles per-stack bandwidth over HBM3, and it does something more interesting than just “go faster”: it fundamentally changes who gets to design part of the memory stack.
SNIA announced StorageAI on August 4, 2025, describing it as an open standards project for efficient data services related to AI workloads, built on industry-standard, non-proprietary, vendor-neutral approaches.
Over the past few months, the AI infrastructure conversation has taken an unmistakable turn: upward.
UALink defines an open, memory-semantic, scale-up interconnect that allows accelerators to perform load, store, and atomic operations across the fabric, not merely send messages to each other.